DFT Engineer Intern

Astera Labs · San Jose, CA or Toronto, Ontario, Canada - Internship · On-site

About Astera Labs

Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our products combine complex digital logic, high-speed interfaces, embedded control, and test infrastructure to deliver reliable connectivity across demanding systems.

The opportunity

Join the Design-for-Test (DFT) team and help make complex silicon easier to test, debug, and manufacture. You’ll learn how DFT structures and methodologies are designed, implemented, verified, and analyzed across the chip development flow.

This internship is designed for someone who enjoys connecting digital design fundamentals with practical silicon-quality challenges. You’ll work with experienced engineers on a meaningful project involving test structures, patterns, coverage, simulation, or debug, while collaborating with RTL design, physical design, verification, validation, and manufacturing-test teams.

What you’ll do

• Learn the product domain, DFT flow, project goals, development environment, and processes needed to contribute effectively.

• Support DFT architecture and implementation activities for digital designs, including scan, test compression, memory test, built-in self-test, boundary scan, JTAG, and design-for-debug structures.

• Work with RTL, netlists, constraints, test modes, clocking, resets, and power intent as needed to understand and implement test requirements.

• Generate, run, and analyze structural test or ATPG patterns and investigate coverage, fault, rule, or simulation results.

• Support scan insertion, test-logic validation, MBIST/BIST configuration, test-mode checks, or related DFT flow activities under engineering guidance.

• Run simulations and, where applicable, gate-level or X-propagation checks to debug DFT behavior and identify unexpected or uninitialized signals.

• Analyze logs, reports, waveforms, coverage results, and pattern failures to identify root causes and recommend next steps.

• Develop or improve scripts and automation for DFT setup, pattern generation, regression execution, report parsing, or result analysis.

• Collaborate with RTL, verification, physical design, silicon, validation, and manufacturing-test teams to communicate issues and track corrective actions.

• Participate in code and flow reviews, technical discussions, issue tracking, documentation, and project planning.

• Deliver assigned DFT work in a usable state and explain what was implemented, verified, or improved and how it supports the product flow.

• Present your project, results, and key learnings at the end of the internship.

What you bring

• Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.

• Foundational understanding of digital logic, RTL, computer architecture, semiconductor design, or hardware verification.

• Programming or scripting experience in one or more of Verilog, SystemVerilog, Python, Tcl, Perl, C, C++, or a comparable language.

• Curiosity about how chips are tested and debugged and a methodical approach to analyzing technical evidence.

• Comfort learning in a Linux environment and working with command-line tools, source control, and technical documentation.

• Ability to organize priorities, ask focused questions, communicate progress and blockers, and follow through on commitments.

• Self-motivation, learning agility, professionalism, and a collaborative mindset.

Helpful experience

• Scan chains, scan compression, ATPG, fault models, fault coverage, pattern generation, or test-point insertion.

• MBIST, BIST, boundary scan, JTAG, IEEE 1149.1, design-for-debug, or manufacturing-test concepts.

• Verilog/SystemVerilog RTL simulation, gate-level simulation, assertions, lint, or X-propagation analysis.

• DFT or EDA tools, test-mode configuration, clock observation, reset architecture, or power-aware verification.

• Python, Tcl, Perl, or shell scripting for automation, report parsing, regressions, or data analysis.

• PCIe, CXL, Ethernet, SERDES, retimers, SoC design, or other high-speed connectivity technologies.

• Git, Jira, Confluence, or similar collaborative engineering workflows.

Internship experience and compensation

This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.

Equal opportunity

Astera Labs is committed to providing equal employment opportunities to all applicants and employees. We value diverse perspectives and consider qualified candidates without regard to legally protected characteristics.