Design Verification Engineer Intern

Astera Labs · San Jose, CA · Internship · On-site

About Astera Labs

Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our Hardware Engineering teams design and validate high-performance products that connect processors, accelerators, memory, and network fabrics.

The opportunity

Join the Design Verification team and help validate digital designs before and after silicon. You’ll learn the team’s verification flow, develop and run tests, analyze simulations and waveforms, and contribute to the regressions and coverage that help ensure products behave as intended.

This internship is designed for someone who enjoys understanding how a design should work, creating experiments that exercise it, and investigating the evidence when results differ from expectations. You’ll work with experienced verification and design engineers on a meaningful project with visible product impact, while building practical skills in digital design verification and semiconductor development.

What you’ll do

Learn the product domain, assigned project, verification environment, test flow, and tools needed to contribute effectively.
Read specifications and design documentation to understand functionality, interfaces, corner cases, and verification requirements.
Develop or extend simulation tests and verification components under engineering guidance, using SystemVerilog, UVM-style methodologies, Python, or related tools.
Run simulations and regressions in a Linux environment using the team’s submission scripts, workspace setup, and test definitions.
Analyze test logs, errors, assertions, and simulation output to identify failures and determine whether the issue is in the test, environment, design, or infrastructure.
Use waveform-debug tools such as Verdi or DVE to inspect signal behavior and explain the sequence of events leading to a failure.
Add or update tests, test definitions, regression lists, manifests, and supporting scripts to improve coverage and confidence in the design.
Review coverage results and help identify meaningful gaps in functional or code coverage.
Collaborate with design, firmware, validation, and other engineering teams to communicate findings, reproduce issues, and track corrective actions.
Participate in code reviews, technical discussions, issue tracking, documentation, and project planning.
Take ownership of an assigned verification project, deliver the work in a usable state, and explain what was verified and how it supported the product flow.
Present your project, results, and key learnings at the end of the internship.

What you bring

Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.
Foundational understanding of digital logic, computer architecture, RTL, hardware interfaces, or software development.
Programming experience in one or more of SystemVerilog, Verilog, Python, C, C++, or a comparable language.
Curiosity about how complex digital designs work and a methodical approach to testing assumptions and debugging failures.
Comfort learning in a Linux environment and working with source control, command-line tools, and technical documentation.
Ability to organize priorities, ask focused questions, take ownership of deliverables, and communicate progress and blockers clearly.
Persistence, learning agility, and a collaborative mindset in an environment where verification work requires iteration and investigation.

Helpful experience

SystemVerilog, UVM, constrained-random testing, assertions, scoreboards, monitors, drivers, or functional coverage.
RTL design or verification using Verilog, SystemVerilog, or similar hardware description languages.
Simulation and waveform-debug tools such as VCS, Verdi, DVE, or related EDA tools.
Python or shell scripting for test generation, regression management, log parsing, or data analysis.
Familiarity with simulation regressions, test manifests, coverage databases, or CI/test infrastructure.
Exposure to PCIe, CXL, Ethernet, SERDES, memory systems, SoC design, or other high-speed connectivity technologies.
Git, Jira, Confluence, or similar tools for collaborative engineering workflows.

Internship experience and compensation

This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.

Equal opportunity

Astera Labs is committed to providing equal employment opportunities to all applicants and employees. We value diverse perspectives and consider qualified candidates without regard to legally protected characteristics.

The opportunity

What you’ll do

Learn the product domain, assigned project, verification environment, test flow, and tools needed to contribute effectively.

Read specifications and design documentation to understand functionality, interfaces, corner cases, and verification requirements.

Develop or extend simulation tests and verification components under engineering guidance, using SystemVerilog, UVM-style methodologies, Python, or related tools.

Run simulations and regressions in a Linux environment using the team’s submission scripts, workspace setup, and test definitions.

Analyze test logs, errors, assertions, and simulation output to identify failures and determine whether the issue is in the test, environment, design, or infrastructure.

Use waveform-debug tools such as Verdi or DVE to inspect signal behavior and explain the sequence of events leading to a failure.

Add or update tests, test definitions, regression lists, manifests, and supporting scripts to improve coverage and confidence in the design.

Review coverage results and help identify meaningful gaps in functional or code coverage.

Collaborate with design, firmware, validation, and other engineering teams to communicate findings, reproduce issues, and track corrective actions.

Participate in code reviews, technical discussions, issue tracking, documentation, and project planning.

Take ownership of an assigned verification project, deliver the work in a usable state, and explain what was verified and how it supported the product flow.

Present your project, results, and key learnings at the end of the internship.

What you bring

Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.

Foundational understanding of digital logic, computer architecture, RTL, hardware interfaces, or software development.

Programming experience in one or more of SystemVerilog, Verilog, Python, C, C++, or a comparable language.

Curiosity about how complex digital designs work and a methodical approach to testing assumptions and debugging failures.

Comfort learning in a Linux environment and working with source control, command-line tools, and technical documentation.

Ability to organize priorities, ask focused questions, take ownership of deliverables, and communicate progress and blockers clearly.

Persistence, learning agility, and a collaborative mindset in an environment where verification work requires iteration and investigation.

Helpful experience

SystemVerilog, UVM, constrained-random testing, assertions, scoreboards, monitors, drivers, or functional coverage.

RTL design or verification using Verilog, SystemVerilog, or similar hardware description languages.

Simulation and waveform-debug tools such as VCS, Verdi, DVE, or related EDA tools.

Python or shell scripting for test generation, regression management, log parsing, or data analysis.

Familiarity with simulation regressions, test manifests, coverage databases, or CI/test infrastructure.

Exposure to PCIe, CXL, Ethernet, SERDES, memory systems, SoC design, or other high-speed connectivity technologies.

Git, Jira, Confluence, or similar tools for collaborative engineering workflows.

Internship experience and compensation