Intern, RTL Power Macromodeling Engineer

What You’ll Learn

• Project Overview: AI memory is now the bottleneck of AI systems: power and heat decide how fast models can run. Our lab turns RTL and trace behavior into time-indexed power models that drive a trace-driven power and thermal simulator.
• Skills You’ll Learn:
  • Power macromodeling
  • RTL and SystemC power feature extraction
  • Trace-driven power and thermal simulation

What You’ll Do

Samsung’s Power & Thermal Lab is seeking an RTL focused intern to help build and validate the power models that the simulator runs on real AI memory components.

We are a small, fast‑moving team where direct ownership and minimal busywork empower every member to tackle the same real‑world problems. Working with authentic data, real partners, and production‑grade results, our contributions flow straight into platforms used across the company.

As an intern, you will support research and product teams across multiple projects, including creating and validating IP‑level power macromodels for AI‑memory components. You will work on real projects with tangible results, receive mentorship, and help shape the scope of work in a collaborative environment where hardware, software, and thermal experts work side‑by‑side on next‑generation AI memory technologies.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy

Reports to: SVP, R&D (Power & Thermal Lab)

• Develop IP-level power macromodels for AI memory components such as PHY, memory controller, interconnect, and TSV, using analytical models, lookup tables, FSM, neural networks, and their hybrids.
• Extract activity, value, and state dependent power features from RTL, SystemC, and C simulations.
• Support calibration with synthesis assisted anchors, circuit level references, and measured data.
• Validate your models against RTL and gate level power analysis and silicon, and improve them where they disagree.
• Deliver validated models and regression checks into the trace-driven flow, working with the software engineers on model interfaces.
• Complete other responsibilities as assigned.

What You Bring

• MS or PhD in Electrical and Computer Engineering, Computer Science, or a related field.
• Must have at least 1 academic quarter/semester remaining.
• RTL design and analysis experience (Verilog, SystemVerilog, SystemC), and solid C++ or Python.
• Understanding of dynamic and leakage power in CMOS and interconnect, and the ability to abstract circuit behavior into compact models.
• Curiosity about power, heat, and AI hardware; you like to measure rather than guess.
• Experience with power analysis tools such as PrimeTime PX, StarRC, VCS, or PowerArtist, architecture level modeling tools such as McPAT, CACTI, or Wattch, S-parameters and SPICE, UCIe or high speed I/O or 2.5D packaging, preferred
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.