FPGA Design Verification Intern
- Pay
- CA$95k–100k/yr
- Deadline
Job Details:
Job Description:
Altera is responsible for High-Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA validation and debugging.
As an FPGA Design Verification Intern, You will be responsible for verifying Altera IPs such as PCIe, Ethernet, Search and DR.
Key responsibilities include:
- Help in Design, Verification and hardware debug/bring-up of features
- Scripting DV development flow and automation
- IP releases and rollout support
- Interactions with local and remote teams as well as customers
- Regression triaging, debug and bug closures
Our compensation is designed to reflect the Canadian labour market. The actual salary offered may vary based on several factors, including the position’s location, as well as the candidate’s experience, skills, training, and job-specific knowledge. In addition to base salary, we offer performance-based incentive opportunities that reward both individual contributions and overall company success.
Estimated Salary Range: $95K – $100K CAD
We use artificial intelligence to screen, assess, or select applicants for the position. This posting is for an existing vacancy. Canadian work experience is not required for this role. Applicants must be eligible for any required Canada export authorizations.
Qualifications:
Minimum Qualifications:
- The candidate must be pursuing a Bachelor’s Degree in Computer Engineering, Engineering Science, Computer Science, Math, Electrical Engineering or equivalent
- 3+ months of experience in Digital logic hardware (e.g. System Verilog, Verilog and/or VHDL) design or verification
- 3+ months of experience in Software programming or scripting (e.g. C/C++ and/or Python)
Preferred Qualifications:
- Familiarity with FPGA development flows and tools such as Quartus
- Strong analytical and problem-solving skills