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The opportunity: Work term of 4 months starting in January 2027.

Ciena's Wavelogic family of products is widely used in optical fiber transmission solutions and contributes to the advancement of high-speed circuits for broadband fiber-optic modems. This co-op role focuses on analog layout design for advanced high-speed analog circuits in deep-submicron CMOS and/or BiCMOS technologies, including ADC, DAC, and PLL designs. The work is performed under the oversight of a principal layout engineer in close collaboration with team members.

How you will make an impact:

Carry out layout feasibility studies on various circuit designs in collaboration with senior analog designers, considering trade-offs and team discussions.
Create layouts of assigned analog blocks using floor planning, placement, and routing.
Conduct verification checks including DRC, LVS, EM, and IR to ensure layout quality.
Investigate new features in layout tools and processes to enhance productivity.
Provide regular status updates, participate in team meetings, and share experiences with the group.

The must haves:

Education: Actively enrolled in a degree program in Electrical Engineering or related field,
Experience: Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices.
Knowledge of layout techniques for Floor Planning, device matching, minimizing parasitics, shielding, EM, and IR drop.
Experience in custom layout design of Analog/Mixed Signal designs (e.g., Opamp, Current Mirror).
Familiarity with semiconductor manufacturing processes and foundry technologies.
Experience in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre).
Knowledge of how to interpret DRC and LVS reports.

Nice to haves:

Scripting skills in SKILL.
Team collaboration skills, a positive approach, and ability to integrate into an existing team culture.
Communication and interpersonal skills to collaborate with cross-functional teams.
Analytical and problem-solving skills to identify and address layout-related issues efficiently.
Attention to detail to maintain accuracy and quality in layout designs.
Ability to work in a fast-paced, dynamic environment and adapt to changing project requirements.
Ability to identify failure-prone circuit and layout structures and work with circuit designers to resolve problems.

Pay Range: The hourly rate for this position is $25.00 - $34.00

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.